发明名称 LINE-BACK CONTROL SYSTEM FOR CACHE MEMORY
摘要 PURPOSE:To share resources between line-back and line transfer jobs and to reduce a hardware medium by using a mode control circuit to secure start/ interruption/restart functions for transfer of line-back data. CONSTITUTION:When a line-back job is needed at the time of a cache mistake, data read out of a cache memory 1 in 16 times for each transfer unit are stacked in a data stack 3 via an ECC circuit 2 after 2 cycles. Then a line-back job is carried out through a bidirectional bus 14 set in a line-back permission mode. If the preparations are ended for the line transfer of a main memory 11 at a time point when the transfer is finished with a 13th line-back transfer unit, the bus 14 is switched to a line-back permission mode again. Then remaining line-back transfer units in the stack 3 are transferred to a main memory writing stack 10. In such a way, the bus 14 and the circuit 2, etc., are shared for both line and line-back transfer jobs so that the quantity of hardware is reduced.
申请公布号 JPS63180153(A) 申请公布日期 1988.07.25
申请号 JP19870011888 申请日期 1987.01.21
申请人 HITACHI LTD 发明人 YAMAMOTO AKIO;SHIBATA AKIO;KUBO KANJI
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
主权项
地址