发明名称 ISOLATION METHOD OF DIELECTRIC FOR SEMICONDUCTOR DEVICE
摘要 PURPOSE:To reduce the labor hour required for a dielectric isolation work and cost by continuously executing a removal process by the paper etching treatment of a damage layer formed in an isolation trench in an Si substrate and an insulating-layer forming process in the same furnace. CONSTITUTION:Reactive ion etching treatment is executed to the surface of an Si substrate to shape an isolation trench 31. A damage layer 35 is formed onto the inner surface of the isolation trench 31 at that time. The substrate 30 is inserted into a diffusion furnace, paper etching treatment is carried out in the diffusion furnace, and the layer 35 on the inner surface of the isolation trench 31 is removed. The substrate 30 is oxidized and treated in the diffusion furnace left as the substrate 30 is inserted. An insulating layer 32 is shaped onto the inner surface of the isolation trench 31 through the oxidation treatment. The inside of the isolation trench 31 in the substrate 30 is filled with poly Si, and each element region is isolated electrically. According to the method, the trench 31 is not contaminated by an etchant and an impurity, etc., thus reducing the labor hour required for dielectric isolation work and cost.
申请公布号 JPS63178542(A) 申请公布日期 1988.07.22
申请号 JP19870011064 申请日期 1987.01.19
申请人 ROHM CO LTD 发明人 YAMAMOTO NORITOSHI
分类号 H01L21/76 主分类号 H01L21/76
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