发明名称 REPLACEMENT CONTROL SYSTEM FOR BUFFER MEMORY
摘要 PURPOSE:To improve the hit ratio of a buffer memory by forming two replacement controlling bit in each address storage word in a directory memory, specifying a replacing row so that a degenerated low is not selected and specifying a blank row as a replacing row with priority. CONSTITUTION:When it is defined that two control bits formed in each address storage word are bits R0, R1 and the lowest undegenerated row bit is a reference R0, the reference R0 is compared with the bit R1 in each row in case of determining a replacing row, and the coincident smallest row is selected as the replacing row. The bit R1 of each degenerated row is controlled so that the compared result is always different. Consequently, the degenerated row is not selected as the replacing row. Since the reference R0 is registered as the bit R1 of a row deleted by canceling operation, the row is selected as a replacing row with priority.
申请公布号 JPS63178354(A) 申请公布日期 1988.07.22
申请号 JP19870008922 申请日期 1987.01.20
申请人 HITACHI LTD 发明人 ISHIYAMA AKIRA
分类号 G06F12/12 主分类号 G06F12/12
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