| 摘要 |
PURPOSE:To increase the working speed of a data transmission circuit together with reduction of its scale by controlling the internal state of a transfer control circuit and the output to the adjacent stage based on the two inputs given from the adjacent stage and the internal state of its own stage and at the same time constituting a transfer control circuit with a single transfer element against a single stage of a data latch. CONSTITUTION:No significant data is not held by each data latch together with an internal state signal the inverse of qi and input/output signals the inverse of Gi, Ri, gi and ri kept at '1' in an initial state where a reset signal is inputted. Under such conditions, i.e., when the inverse of qi=1 is satisfied, the corresponding state is held and the outputs the inverse of gi and ri to be applied to the next stage are kept at '1' as long as no transmission request is received from the preceding state, i.e., unless the signal the inverse of Gi is set at '0'. if a transmission request is received from the preceding stage under such conditions, i.e., when the inverse of qi=1 is satisfied, the output of a NAND circuit 52 is set at '1' by said request the inverse of Gi=0 and the data received is held by a latch Li as the signal the inverse of qi.
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