发明名称 SYMBOL LAYOUT SYSTEM FOR LOGIC CIRCUIT DIAGRAM
摘要 PURPOSE:To obtain an easy-to-see logic circuit diagram by dividing the symbols of unit component elements into groups in response to function blocks and at the same time controlling the positional relationships among those symbols to decide these relationships according to signal flows. CONSTITUTION:An arithmetic processor 2 stores logic circuit information of a macrocircuit block level supplied from an input/output device 1 in a data memory 3 together with the logic circuit information of a physical parts level. A symbol group forming mechanism 5 of an automatic layout mechanism 4 for logic circuit diagram symbols divides the symbols of physical parts contained in the logic circuit information of the physical parts level into groups in accordance with the symbols contained in said logic circuit information. Then these group information are added to said logic circuit information together with the position information on the corresponding macrocircuit information. A level sorting mechanism 6 in the mechanism 4 decides the layout positions for the symbols of the unit component elements in the symbol groups according to the order of flows of selected signals.
申请公布号 JPS63177268(A) 申请公布日期 1988.07.21
申请号 JP19870009413 申请日期 1987.01.19
申请人 NEC CORP 发明人 NAKAMURA IZUMI;IWASE MASAKAZU;IIJIMA KAZUYUKI;IMAI RUMIKO
分类号 G06F17/50 主分类号 G06F17/50
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