发明名称 CONTROL CIRCUIT FOR DIGITAL SAMPLE RATE CONVERSION
摘要 <p>PURPOSE:To obtain a data scarcely having an error and a quantization noise, by dividing a period of a first sampling clock into plural periods, sampling it by a second sampling clock, detecting a time shift of both these clocks, and eliminating an undesirable influence of stuffing. CONSTITUTION:A coefficient K and (1-k) of the first and second sampling clocks outputted from ROMs 25, 26, respectively correspond to a phase difference of both sampling timings. Also, the coefficient K and (1-K) are supplied to one input ends of multiplying circuits 32, 33 respectively. The circuit 32 between them generates xn-1.K by multiplying K by a digital data xn-1 sampled by the first sampling clock. On the other hand, the circuit 33 obtains xn (1-K) by multiplying the coefficient (1-K) by a sampled digital data xn. Output data of these circuits 32, 33 are added, the equation is calculated, and a digital data y<m> sampled by the second sampling clock is outputted from a terminal 35.</p>
申请公布号 JPS63177619(A) 申请公布日期 1988.07.21
申请号 JP19870009283 申请日期 1987.01.19
申请人 TOSHIBA CORP 发明人 SAKAMOTO NORIYA;YAMADA MASAHIRO
分类号 H03M1/66;H04L7/00 主分类号 H03M1/66
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