发明名称 VECTOR CODING SYSTEM
摘要 PURPOSE:To attain vector quantization by a few reference vectors by folding an input vector at a plane perpendicular to each reference vector to approach an input vector to a center vector and extracting a bit of information on which side of symmetrical planes the input vector exists in the case of the folding as a vector index. CONSTITUTION:In the case of the inner product of (X0, R0)<0, where X0 is the vector of mean value to be separated and R0 is a 1st reference vector R0, the reference vector R0 is outputted from a gate circuit 15, the output of an accumulator 13 and the inner product are multiplied by a multiplier 16 and the result is subtracted from the vector X0 retarded by a delay circuit 17 by a coefficient 2. That is, the conversion output X1 of a conversion stage block 10 is expressed as X1=X0-2I0.(X0, R0)R0. The vector X1 is converted similarly as X2, X3,..., XN succeedingly and index information I1, I2,..., IN-1 are outputted form each conversion stage. Thus, the number of reference vectors is minimized as soon as possible and the vector coding system close to an ideal characteristic is formed.
申请公布号 JPS63176022(A) 申请公布日期 1988.07.20
申请号 JP19870006173 申请日期 1987.01.16
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SUZUKI YUTAKA;WATANABE YUTAKA;HASHIMOTO HIDEO
分类号 H03M13/00;G06F17/16 主分类号 H03M13/00
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