发明名称 INPUT CIRCUIT FOR DIGITAL PHASE LOCKED LOOP
摘要 <p>PURPOSE:To operate a digital phase locked loop in an excellent way by providing 1st and 2nd filtering means and a selection means and obtaining a stable output digital signal even when noise is included in an input analog signal. CONSTITUTION:An output signal is increased/decreased in the unit of 1 bit only in the 1st filtering, means F1 and no noise included in the input analog signal is outputted. In the 2nd filtering means F2, a signal nearly averaging the input signal over a prescribed period is outputted, then the noise in the input analog signal is reduced remarkably. Moreover, in using the 1st and 2nd filtering means F1, F2 in cascade, the noise reduction effect of the filtering means is overlapped.</p>
申请公布号 JPS63176018(A) 申请公布日期 1988.07.20
申请号 JP19870007904 申请日期 1987.01.16
申请人 YAMAHA CORP 发明人 IIJIMA KENZABURO;HAYASHI YOSHINORI
分类号 H03L7/06;H03H17/00;H03H17/02;H03M1/00;H03M1/08 主分类号 H03L7/06
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