发明名称 ARITHMETIC PROCESSING UNIT
摘要 PURPOSE:To attain arithmetic processing during accessing to a memory and to shorten a processing time by providing a means for controlling a data memory interface by a field which is part of instruction. CONSTITUTION:A means for controlling a read data input timing at the time of accessing to read a memory according to a program is provided to obtain independently the timing of in the read data input from the memory and the timing in the read data input on the program. Therefore, at the time of reading, parallel operation of the memory access and the arithmetic processing and also a high speed processing can be attained. In circuit constitution, at least one read data storing register 6 is provided, a register 9 for inputting at the time of accessing to read the memory is designated, and the processing for inputting to the designated register 9 and other arithmetic processing are executed in parallel.
申请公布号 JPS63175952(A) 申请公布日期 1988.07.20
申请号 JP19870005941 申请日期 1987.01.16
申请人 HITACHI LTD 发明人 OGURA TOSHIHIKO;KUBOTA KAZUMI;ENOMOTO HIROMICHI;FUJIGAMI YOSHIHIRO
分类号 G09G5/393;G06F7/00;G06F12/00;G06T11/20;G09G1/02;G09G1/06;G09G5/00;G09G5/36;G09G5/395 主分类号 G09G5/393
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