发明名称 INTERFACE CIRCUIT FOR DATA COMMUNICATION
摘要 PURPOSE:To relieve the load of an external host processor by providing a reception FIFO circuit and a comparator comparing data representing the end of sent data. CONSTITUTION:In a binary synchronous protocol BISYNC as a communication protocol, a code representing the end of a transmission block is an end of transmission block ETB and a block check character BCC follows thereafter. A value 17H (hexadecimal expression) of the ETB is stored in advance to a comparator 105 and when the ETB is detected in the received data, the output of the comparator 105 is active, a reception FlFO status circuit 103 and a control circuit 104 are initialized and the BCC is eliminated from the reception FIFO circuit 101. Thus, the load of an external host processor is relieved.
申请公布号 JPS63176047(A) 申请公布日期 1988.07.20
申请号 JP19870007566 申请日期 1987.01.16
申请人 NEC CORP 发明人 YONEZU KAZUYA
分类号 H04L13/08;H04L13/00;H04L13/18;H04L29/00;H04L29/02 主分类号 H04L13/08
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