发明名称 PROCESS FOR MANUFACTORING AN ELECTRICAL CAPACITOR WITH POLYETHYLENE TEREPHTHALATE AS A DIELECTRIC, ESPECIALLY FOR USE AS A SOLDERABLE CHIP ELEMENT
摘要 An electric capacitor formed of dielectric layers provided on at least one side with metal layers with coatings, and wherein the layers are formed of partially crystallized and pre-shrunk polyethylene terephthalate. The coatings are alternately electrically conductively connected to metal layers applied by the Schoop process with opposing polarity to end faces of the capacitor body. The dielectric layers are arranged to form a stack or are deformed to form a flat-pressed winding. The polyethylene terephthalate dielectric layers have a degree of crystallization of at least 50%, in particular at least 55%, measured by differential thermo-analysis in order to determine the melting point enthalpy. In a method for production of such a capacitor, the capacitor bodies provided with the metal layers are subjected to an additional heat treatment in which the temperature is increased from room temperature to a final temperature of 200 DEG to 250 DEG C. for 1 to 5 hours. This final temperature is held for a period of 1 to 65 hours, where the length of this holding time is inversely proportional to the final temperature.
申请公布号 EP0162144(B1) 申请公布日期 1988.07.20
申请号 EP19840115615 申请日期 1984.12.17
申请人 SIEMENS AKTIENGESELLSCHAFT BERLIN UND MUNCHEN 发明人 HARTMUT, MICHEL, DR. RER. NAT.
分类号 H01G4/18;H01G13/00;(IPC1-7):H01G4/18 主分类号 H01G4/18
代理机构 代理人
主权项
地址