发明名称 Phase lock circuit.
摘要 Phase lock circuit for generating a periodical reference signal having a variable frequency, locked to the frequency of a sequence of electrical pulses corresponding to information (RD) read out from a movable magnetic media where information is recorded in phase modulation as to a nominal frequency, comprising a phase comparator (1) for generating a pulsed signal (PUP) having width proportional to the lead error of the electrical pulses as to the periodical reference signal, logical circuits for generating a pulsed signal (P DOWN) having width proportional to the lag error of the electrical pulses as to the periodical reference signal (VFO), a plurality of low pass filters (7, 25-21, 26) having two poles and one zero and selectable (LFSEL) in mutually exclusive way for generating a continuous signal having variable voltage as a function of said pulsed error signals, a decoupling element (15) having the function of voltage follower for inputing the continuous signal to a variable frequency oscillator (3), temperature compensated, which generates the periodical reference signal, the selection of each one of the low pass filters determining an optimized frequency response of the phase lock circuit for each of different working conditions defined by different nominal frequencies of information recording.
申请公布号 EP0274591(A1) 申请公布日期 1988.07.20
申请号 EP19870116273 申请日期 1987.11.05
申请人 HONEYWELL BULL ITALIA S.P.A. 发明人 VITIELLO, PAOLO
分类号 G11B20/14;H03L7/089 主分类号 G11B20/14
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