| 摘要 |
PURPOSE:To control the waveform within a prescribed cycle time by reading a desired data into a shift register by a prescribed bit number in parallel and outputting the signal serially sequentially in a prescribed timing synchronously with a preset signal and a single phase clock signal. CONSTITUTION:When a selection code signal for waveform selection is supplied, test data D0-D5 corresponding to the signal are fed from a data memory DM to a shift register SFTR in parallel. A clock signal outputted from a clock generator CLKG and a preset signal outputted from a preset decoder circuit PDEC are fed to the shift register SFTR and the test data is outputted serially to an analog driver ADRV synchronously with the cycle of the clock signal or its leading. Thus, the waveform is controlled surely and simply within a prescribed cycle time corresponding to the cycle of the clock signal.
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