发明名称 |
Method for generating logic circuit data |
摘要 |
In automatic development of the higher hierarchic logic into the lower hierarchic logic in a hierarchic logic designing, identification codes are beforehand assigned to logic components of the higher hierarchic logic, and the identification codes are also assigned to the lower hierarchic logic data when developing the higher hierarchic logic into the lower hierarchic logic in order to establish correspondences between the higher and lower hierarchic logic, thereby allowing a higher-speed logic compare operation with respect to a design change on the higher or lower hierarchic logic and enabling the automatic update of the lower hierarchic logic by use of the higher hierarchic logic as the master.
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申请公布号 |
US4758953(A) |
申请公布日期 |
1988.07.19 |
申请号 |
US19870102771 |
申请日期 |
1987.09.23 |
申请人 |
HITACHI, LTD. |
发明人 |
MORITA, MASATO;IKARIYA, YUKIO;SAKATAYA, YOSHINORI;MIYOSHI, MASAYUKI |
分类号 |
G06F17/50;G06F19/00;G06T5/00;(IPC1-7):G06F15/60 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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