发明名称 SEMICONDUCTOR WAFER GRINDING DEVICE
摘要 PURPOSE:To reduce a grinding amount at each stage, by a method wherein first fourth spindle, having grinding stones for first stage rough grinding, second stage rough grinding, intermediate grinding, and finish grinding, respectively, are mounted to a one pass system. CONSTITUTION:A first spindle 1 to which to attache grinding stone 1a effecting first stage rough grinding, a second spindle 6 to which to attache effecting second stage rough grinding stone 6a, a third spindle 7 to which to attache a grinding stone 7a effecting intermediate grinding, and a fourth spindle 8 to which to attache a grinding stone 8a effecting finish grinding are disposed to a one pass system semiconductor wafer grinding device. Grinding is applied on a semiconductor wafer 3 with thickness (a) secured to a chuck table 14 so that thickness is decreased, in order, from (b) to (e) by using grinding stones 1a, 6a, 7a, and 8a, the grinding grain sizes of which are decreased, in order named. This constitution reduces a grinding amount at each stage to reduce a load on the wafer, and enables prevention of the occurrence of breakdown and crack due to grinding.
申请公布号 JPS63174855(A) 申请公布日期 1988.07.19
申请号 JP19870007574 申请日期 1987.01.16
申请人 NEC CORP 发明人 TERADA HITOSHI
分类号 B24B7/02;H01L21/304 主分类号 B24B7/02
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