发明名称 ERROR FLAG CONTROL CIRCUIT FOR DIGITAL REPRODUCING DEVICE
摘要 PURPOSE:To set an error flag regardless of any state of the reproduction data by setting the error flag values of all sub-blocks at '1' in a period during which a data memory is read out and the data on the next frame is written. CONSTITUTION:An address generating circuit 8 which produces the same address value as that of a data memory 1, an error flag write control circuit 9 which sets an error flag '1', and a flag memory 12 which stores the error flag are provided in the data unrecorded sections set before the valid data is reproduced with use of a head switch signal. Then both memories 1 and 12 are counted when the memory 1 is read. If the count value is kept within a range of correcting capacity of a horizontal error correcting circuit 2, an error block is corrected. In such a way, the flag '1' set on the memory 12 is controlled according to the reproduction state even though the error flag set on the memory 1 is not fixed due to the state of the reproduction data. Then the errors are corrected based on the result of said control of the flag '1'. Thus the errors are surely corrected.
申请公布号 JPS63175272(A) 申请公布日期 1988.07.19
申请号 JP19870006124 申请日期 1987.01.16
申请人 TOSHIBA CORP 发明人 IKEDA HIDENARI
分类号 G11B20/18 主分类号 G11B20/18
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