| 摘要 |
PURPOSE:To vary the branching of a data in one frame, the occupied slot width of a control signal, transmission speed, and a cycle, by adding a control signal output possible/impossible signal on the port address of an address control memory. CONSTITUTION:The switching of its own port main signal and control signal transmittable/receivable signals 18 and 19 is performed by using a part of a port designation address 12. The port designation address bus 12 can be varied by the rewrite of a memory from the outside because it is designated by the address control memory. When its own port main signal and the control signal transmittable/receivable signals 18 and 19 are activated, a main signal output data 13 or a control signal output data 20 is outputted to a multiple bus 14, and a main signal input data 16 or a control signal input data 16 is inputted from the multiple bus 14.
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