| 摘要 |
PURPOSE:To keep the voltage level of a signal inputted in a delay circuit of next stage nearly constant by giving level shift quantity which cancels the level shift quantity of the input signal to the shift part of the voltage level of the input signal. CONSTITUTION:When number of horizontal scanning line signal of the input signal S1 is inputted in an input terminal 1, the voltage valve of a pulse signal SP inputted in the input terminal 9 is zero, so that a level shift circuit 10 outputs the input signal S1 as it is. Meanwhile, when the odd number of scanning line signal of the input signal S1 is inputted, the voltage valve of the pulse signal SP becomes (Vh), so that the input signal S1 is level-shifted by the voltage Vh to be outputted. As a result, the signal 83 inputted in a 1H delay circuit 2 becomes a signal where the shift of a DC level is denied every horizontal period of the input signal 51. The output signal 54 of the 1H delay circuit 2 is subtracted from the inverse signal of the pulse signal SP in the level shift circuit 11 and the signal whose DC level returns to the former one is outputted.
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