| 摘要 |
PURPOSE:To stabilize a signal which is inputted in a second PLL and to make it precisely lock in the second PLL by making the dividing ratio of a first PLL smaller than that of the second PLL and the lock range of the first PLL wider than that of the second PLL. CONSTITUTION:The first PLL 20 locks with an HSYNC signal outputted from an HSYNC separation circuit 2 and actuates, and the second PLL 21 locks with the HSYNC signal or the output from the first PLL and actuates. In the first PLL 20, the dividing ratio of a divider 25 is smaller than that of the divider 29 in the second PLL 21 and the lock range by LPF 23 and VCO 24 is wider than that of the second PLL 21. A switching switch 34 inputs the output from the first PLL 20 in the second PLL 21 near a vertical period signal VSYNC and directly inputs the HSYNC signal in the second PLL 21 except the VSYNC according to the output from a V timing POM 33.
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