发明名称 SYSTEM FOR READING OUT TIMER SIMULTANEOUSLY IN MULTPLEX PROCESSOR SYSTEM
摘要 <p>PURPOSE:To confirm whether or not each processor execute a processing in a correct order relation, by reading out the value of the timer of each processor simultaneously corresponding to a bit of command information outputted from a command information generating means, and storing it in a timer register. CONSTITUTION:A multiplex processor system is provided with plural processors 1, 2, and 3 having the same functions, and a controller 4 which controls each processor. The controller 4 supplies the bit of command information to the timer registers 102, 202, and 302 of the processors 1-3 appropriately via signal line 5 to confirm whether or not each processor executes respective processing in the correct order relation. As a result, the register 102, 202, and 302 can read out and stored the values of the timer 101, 201, and 301 simultaneously corresponding to the bit of a command information. Stored timer values are supplied to and compared at the controller 4, and when the difference of the timer values is less than a prescribed value, it is possible to confirm that each processor can execute the processing in the correct order relation.</p>
申请公布号 JPS63173154(A) 申请公布日期 1988.07.16
申请号 JP19870004755 申请日期 1987.01.12
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SHIOZAWA TSUNEMICHI;HIRAMATSU TAKUYA;HIRANO MASANORI
分类号 G06F15/16;G06F1/14;G06F15/17;G06F15/177 主分类号 G06F15/16
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