发明名称 DATA TRANSMISSION CIRCUIT
摘要 PURPOSE:To improve the following character of a reception clock for the fluctuation of a transmission clock by supplying a frame synchronizing signal or a bit decided as the frame synchronizing signal with data read out according to a data volume detecting means and transmitting the data as it is. CONSTITUTION:Inputted data is written in a bit memory means 15 by a write clock and read out by a read out clock which is asynchronous with the write clock, but the volume of the read out data is changed according to the output of the data volume detecting means 16. In a transmission data generating means 17, the deviation of the write clock for the read out clock is absorbed in a bit unit by supplying the frame synchronizing signal or the bit decided as the frame synchronizing signal with the data read out according to the output of the data volume detecting means 16 and transmitting the data as it is. Thus, the following character of the read out clock in a clock reception circuit for the fluctuation of the write clock in a clock transmission circuit is improved.
申请公布号 JPS63169150(A) 申请公布日期 1988.07.13
申请号 JP19870000707 申请日期 1987.01.06
申请人 FUJITSU LTD 发明人 AMARI HIDETOSHI
分类号 H04J3/06;H04L7/00;H04L7/08;H04L13/08;H04L13/16 主分类号 H04J3/06
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