发明名称 PARALLEL/SERIAL CONVERSION CIRCUIT
摘要 PURPOSE:To constitute the titled circuit with lease circuit elements by constituting the titled circuit with a signal selection circuit and an output holding circuit instead of a shift register to hold a parallel data. CONSTITUTION:The titled circuit comprises a latch circuit 1 to hold parallel data by a latch pulse 6, a signal selection circuit 2 to sequentially select parallel data held preliminarily in a counter initialized by a reset signal 13 by using a selection signal generated by supporting clock pulses 13 equal to the parallel data in number, and an output holding circuit 3 to hold a one-bit data selected by the signal selection circuit 2 at every clock pulse 12 which is initialized by the reset signal 13. As a result, the titled circuit can be constituted with less number of circuit elements.
申请公布号 JPS63169128(A) 申请公布日期 1988.07.13
申请号 JP19870000651 申请日期 1987.01.05
申请人 NEC CORP 发明人 USAMI MINORU
分类号 H03M9/00 主分类号 H03M9/00
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