发明名称 CMOS GATE ARRAY
摘要 PURPOSE:To set output currents variably by arranging a plurality of P channel transistors and N channel transistors each connected by wirings selectively as the P channel transistors and N channel transistors constituting a CMOS output buffer. CONSTITUTION:Desired output currents can be selected by a wiring process, and the combination of P channel transistors (Pch Tr) 12-15 and N channel transistors (Nch Tr) 22-25 used as output buffers for an actual gate array can be selected freely. Only the P channel transistor such as numeral 12 is employed as the Pch Tr, and gate input terminals for other Pch Trs 13-15 are connected to the positive power terminal 40 side. On the other hand, the Nch Trs 22-24 are used and a gate input terminal for the residual Nch Tr 25 is connected to a negative power terminal 50. According to such selection, arbitrary output-buffer drive capacity can be acquired.
申请公布号 JPS63169742(A) 申请公布日期 1988.07.13
申请号 JP19870002295 申请日期 1987.01.07
申请人 MITSUBISHI ELECTRIC CORP 发明人 NISHITANI KAZUHARU
分类号 H03K19/0948;H01L21/82;H01L21/8238;H01L27/092;H01L27/118 主分类号 H03K19/0948
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