| 摘要 |
PURPOSE:To facilitate the frequency switching and to prevent the production of malfunction of a CPU by clearing a latch circuit when an output of NOR circuit is a high level signal so as to inhibit a clock signal selection function in a clock signal selection circuit thereby outputting a high level signal. CONSTITUTION:In setting a data bit information D0 signal to an optional I/O port, the D0 signal is impressed to an input terminal D of a DFF 17. The switching is executed from a clock signal CLK1 to a CLK2 signal when the D0 signal is at a high level and from the CLK2 signal to the CLK1 signal when at low level. DFFs 20, 22 and OR circuits 21, 24 control the circuit so that the CLK1, CLK2 signals are not respectively fed to terminals 1A, 1B during the switching of the clock signal by a clock signal selection circuit 25. Thus, a high level signal is outputted as the CLK signal at the switching of the clock signal continuously, then a pulse smaller than the minimum period is not outputted from a terminal 1Y.
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