| 摘要 |
PURPOSE:To prevent the level drop of data supplied to paired bit lines without using a boosting circuit by driving each pair of bit lines via a PMOS type flip-flop with no intervention of a selecting MOS transistor. CONSTITUTION:The selecting MOS transistors TR12m and 12n of divided bit line pairs BLm, the inverse of BLm, BLn and the inverse of BLn are provided between two PMOS flip-flops 15m and 15n and a NMOS flip-flop 19 respectively. An end of each of column selecting MOS TR23 and 24 is connected between the flip-flop 19 and the TR12m and 12n connected to one side of each of pairs BLm - the inverse of BLn respectively. While the other end of each of both TRs 23 and 24 is connected to the data lines DL ad the inverse of DL respectively. Thus it is not required to use a boosting circuit for bit line pair selecting signal that drives the TR12m and 12n. As a result, the pattern area is never increased by said boosting circuit to prevent the level drop of the data supplied to the bit line pairs.
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