发明名称 ARRANGEMENT AND DISPLAY SYSTEM FOR LOGIC CIRCUIT DIAGRAM FUNCTION BLOCK
摘要 PURPOSE:To automate the arrangement of function blocks by storing hierarchic circuit connection data, performing initial arrangement according to expected arrangement coordinates of the function blocks by hierarchies, and moving rotational positions according to restriction conditions. CONSTITUTION:An arrangement circuit hierarchy instruction part 102 when receiving an execution circuit name from an input device 101 sends it to a circuit connection data storage part 103 and extracts and sends out arrangement information 401 to a high-order function block arrangement information storage part 104. Then, low-order function blocks with block names 1-6 are extracted and sent to the storage part 103 to extract pieces of arrangement information on the respective blocks, which are sent to a low-order function block information storage part 105. An arrangement alternation algorithm execution part 107 extracts expected arrangement coordinates and sizes of the respective low-order function blocks from the storage part 104 and 105 and arranges the blocks according to them. The arrangement alteration algorithm execution part 107 reads the shortest circuit-to-circuit distance 10 and an overlap deciding method out of a circuit arrangement control condition violation and elimination method storage part 106 to determine and arrange the areas of boxes 1-6, and also move the boxes if there is an overlap.
申请公布号 JPS63167975(A) 申请公布日期 1988.07.12
申请号 JP19870000012 申请日期 1987.01.05
申请人 HITACHI LTD 发明人 MURATA NORIKO;YOKOTA TAKAYOSHI;HAMADA KANMAN
分类号 G06F17/50 主分类号 G06F17/50
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