发明名称 LOGIC CIRCUIT SIMULATION DEVICE
摘要 <p>PURPOSE:To execute the execution of simulation without interruption by sending a command such as an observing point (probe) setting release state value setting or the like as an event to a simulation processor from a control processor during the execution of logical simulation. CONSTITUTION:A control processor 105 is connected to a 2nd dynamic memory section 106 via a 1st bus 110, supplies the input pattern to an object circuit to simulation processors 101, 103 and the even arising as the result from the simulation simulation processors 101, 103 is stored in the 2nd dynamic memory section 106. An interface processor 107 loads in advance an object circuit before the execution of simulation to the 1st dynamic memory sections 102, 104 and the 2nd dynamic memory section 106 via bus I and an input pattern string and a command sorted in the order of time raised during the execution of simulation are loaded to the 2nd dynamic memory section 106.</p>
申请公布号 JPS63168738(A) 申请公布日期 1988.07.12
申请号 JP19870001297 申请日期 1987.01.06
申请人 NEC CORP 发明人 ISOBE KATSUYOSHI
分类号 G06F11/25;G06F11/26;G06F17/50;G06F19/00 主分类号 G06F11/25
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