发明名称 REPLY SUPERVISORY CONTROL SYSTEM
摘要 PURPOSE:To improve the utilizing efficiency of the entire buffer without giving the effect on the signal transmission by providing exclusively a data transmission buffer to send a signal and a timing count buffer for supervising an acknowledge signal, respectively. CONSTITUTION:In sending a signal from one station to the whole country, a transmission buffer t4 is segmented from a pool queue A2 of signal transfer buffer, and enqueued to the transmission queue and a timer registration buffer t5 from a pool queue B of a timer registration control buffer to await the reply, and enqueued to the timer queue tq2. The buffer t4 is restored to the pool queue A2 after the signal is transmitted, and preserved till the reply signal is received or timeout occurs, and restored to the pool queue B.
申请公布号 JPS63167547(A) 申请公布日期 1988.07.11
申请号 JP19860314034 申请日期 1986.12.27
申请人 NEC CORP 发明人 FUJIKAWA WATARU
分类号 H04L29/08;H04L13/00;H04L13/08 主分类号 H04L29/08
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