| 摘要 |
PURPOSE:To prevent the reproduction error of a synchronizing signal, etc., from being generated and to realize an optical system with resulting high reliability, by applying asymmetry correction automatically on the reproducing output of the synchronizing signal recorded in advance keeping a prescribed interval in a track direction. CONSTITUTION:A 1/2 frequency demultiplier 26 forms a bit lock with a very small amount of frequency fluctuation at every bit from a phase locked loop formed at a phase comparator 19, and referring pulse width formed from the bit lock is compared with the pulse width of an arranged output in which the synchronizing signal recorded in advance keeping the prescribed interval in a reproduced track direction is arranged at a binarization comparator 12 at a NAND gate 15 and a NOR gate 16, and the asymmetry error of a detected arranged output is fed back to the binarization comparator 12, and controls the slicing level of the binarization comparator 12, thereby, asymmetry can be corrected automatically.
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