发明名称 VIDEO SIGNAL PROCESSING UNIT
摘要 PURPOSE:To make the titled unit suitable for applications of the memory by using a horizontal synchronizing signal of an input video signal so as to reset a write or read address signal and acting the memory as a variable, delay line in writing or reading the digital video signal of a single clock to/from a time base correction memory. CONSTITUTION:A memory 31 for time base correction is provided and the write into the memory 31 and the readout from the memory 31 with respect to at least a luminance signal in a digital video signal are applied by using a prescribed clock, and the write address signal or the read address signal to/from the memory 31 are reset by using a horizontal synchronizing signal in the luminance signal written in the memory 31. Thus, a first data location is constant at each line and the digitized data by the clock of the subcarrier lock system is arranged vertically on the screen similarly as line-lock and used suitably for memory applications.
申请公布号 JPS63166388(A) 申请公布日期 1988.07.09
申请号 JP19860316146 申请日期 1986.12.26
申请人 SONY CORP 发明人 HARADA SHIGERU
分类号 H04N5/953;H04N5/95;H04N9/89;H04N9/896 主分类号 H04N5/953
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