| 摘要 |
PURPOSE:To improve the step coverage of an upper layer wiring by opening a via hole in a multilayer interconnection structure equal to or more than the width of a lower layer wiring and by locally reducing the thickness of the lower layer wiring at the via hole. CONSTITUTION:A silicon oxide film 1 is formed as a protecting film on a semiconductor substrate wherein semiconductor elements are formed, and the first aluminum layer 2 is formed after a contact hole is opened in the silicon oxide film 1. An insulating film 3 is formed on the aluminum layer 2 and an aluminum film 4 for mask is formed. Then, a photo resist 5 is formed and a via hole is opened by selectively etching the film 4 by using the photo resist 5 as a mask. Then, after the photo resist 5 is peeled, the insulating film 3 is isotropically etched to a thickness of approx. 1/2 by using the film 4 as a mask. Then, the remaining 1/2 thickness of the insulating film 3 is anisotropically etched by using the film 4 again as a mask. Successively, after the film 4 is removed by anisotropic etching, the second aluminum layer 6 is formed. This can easily form a lower layer wiring and can improve the step coverage of an upper layer wiring.
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