| 摘要 |
PURPOSE:To realize an edge detection circuit synchronously with a clock and preventing a mis-output to noise by sampling the data by the clock, using a shift register so as to shift sequentially the data and ANDing n-stage of outputs. CONSTITUTION:Positive logic outputs Q1-Q4 of 1st-4th flip-flops 1-4 go sequentially to logical '1' by an input and a clock, and a leading edge signal Xr is outputted from an AND gate 6 just before the positive logic output Q5 of a 5th flip-flop 5 goes to '1', that is, just before a negative logic output, inverse of Q5 goes to '0'. Conversely, positive logic outputs Q1-Q4 go sequentially to '0' and just before the positive logic output Q5 goes to '0', a trailing edge signal Xf is outputted from an AND gate 7. If noise is superimposed on the input, since logic outputs of five-stages are ANDed, a leading edge detection signal is outputted after the leading of the normal signal being logical '1' for 4 clocks or over. Moreover, since the data is sampled only at the leading of the clock, the data is not affected by the noise superimposed between clocks. |
