| 摘要 |
PURPOSE:To recover the circuit from a fault of disturbed data in a FIFO surely by inputting a marker signal indicating the head of the data to the FIFO (first-in first-out memory) together with the data. CONSTITUTION:A multiplexed serial signal (b) is converted into a parallel signal in a serial/parallel conversion section 1 and inputted to FIFOs 2, 2a by the control of a FIFO state supervisory section 4. The marker signal (c) being logical '1' only at the timing at the head of the data is inputted to the FIFO2 at the same time. When the data stored in the FIFOs 2, 2a is outputted sequentially, the marker signal (g) outputted at the head of the data is confirmed by a marker supervisory section 6 and when the level is not logical '1', it is recognized that the data of the preceding slot is disturbed to clear the data in the FIFOs 2, 2a. Thus, the fault of disturbed data caused by the disturbance of the output clock of the FIFOs 2, 2a is recovered surely.
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