发明名称 MISSING LOCATION POLYNOMIAL GENERATING CIRCUIT
摘要 PURPOSE:To attain large scale circuit integration with small sized hardware capacity by connecting plural number of identical arithmetic circuits each consisting of a multiplier on Galois field, an adder and m-set of register arrays storing its addition output and selector output so as to obtain the multiplication of a specific missing location polynomial and polynomials Ax, Bx. CONSTITUTION:The missing location polynomial lambdax is generated by equation I. At first, a selector section signal is set as S1,2=11 at first at the input of Y1, D input Z0=1 is inputted to X, a C input 0 is inputted to Y and the Y1 being the result of arithmetic operation is inputted to a register string 6. The with the relation of S1, 2=10, the C input 0 is outputted to X, the A input retarding the Z0 by one clock is outputted to Y and the result of arithmetic operation, Z0=1 is inputted to the register array 6 by the next clock. Since the result of operation is 0 on and after the enxt clock, 0 is inputted to the register array 6. After one period, the result of preceding arithmetic operation Z1=Y1*x+1 is outputted from the register array 6. The operation at the input of Y2 is repeated even after the input of Y3 to output the lambdax from the register array 6 from the high order coefficient after the input of Y5.
申请公布号 JPS63164627(A) 申请公布日期 1988.07.08
申请号 JP19860310834 申请日期 1986.12.26
申请人 CANON INC 发明人 IWAMURA KEIICHI;IMAI HIDEKI;DOI YASUTAKA
分类号 H03M13/00 主分类号 H03M13/00
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