| 摘要 |
A frame buffer for high input and output speeds, comprising a number of memory blocks which are supplied with the same address (AD) and the same address transfer signals (RAS, CAS), the data inputs (DE1 to DE4) of the memory blocks (SB1 to SB4) are connected together, the data outputs (DA1 to DA4) are also connected together and all memory blocks are in each case supplied with write signals (W1 to W4) and/or read signals (R1 to R4), which are uniformly offset in time, in each case within one address cycle. <IMAGE>
|
