| 摘要 |
PURPOSE:To stably obtain a RAM backup state without limiting the speed at the time of normal operation by detecting the turning-off of a main power source to slow system clocks. CONSTITUTION:A main power source voltage drop detecting circuit (0V detecting circuit) which detects the drop of the main power source voltage and a system clock varying circuit 2 which slows down system clocks of the circuit by the detection signal are provided. When the main power source is turned on, a device starts from the initial state and performs the normal operation; and when the power source is turned off, this turning-off is detected to bring into the preparation state for RAM backup. In this case, when the drop of the main power source voltage is detected, system clocks are slowed so that the normal operation is sufficiently performed though the voltage slightly drops. When a RAM backup instruction is executed, the system is set to the RAM backup state and data in the RAM is held and the system is the down state. When the main power source is turned on, the RAM backup state is released and the normal operation state is restored. |
