| 摘要 |
PURPOSE:To quickly access a memory by providing a data latch, an error information latch, and a timing controller. CONSTITUTION:If a memory read request signal RD 9 is given, a data memory 1 and an error information memory 2 validates read data and error information data (d) stored in an EDOUT 19 respectively on a data bus 10 after an access time when the address to be accessed is validated on an address bus 11. Read data and stored error information data are stored in a data latch 3 and an error information latch 5 respectively by the timing pulse generated from a timing controller 7. Simultaneously, the access cycle of an external device is terminated. Thus, the access cycle is only the sum of the access time and the data reporting time.
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