| 摘要 |
PURPOSE:To shorten a leading-in time and to output clocks with a stabilized phase by detecting a phase shifted value by means of a shift register at the time of comparing phases and selecting a frequency dividing value in accordance with the phase shifted value. CONSTITUTION:An input signal 100 and shift clock 110 synchronizing with a master clock 180 are inputted to the shift register 120 and latched data are stored in the shift register 120. An output signal 170 and the master clock 180 are inputted to a decoder control circuit 130, and after counting up clocks from the rise of the signal 170 up to 1/2 the number of shifted bits by means of a master clock, a decode enable signal 131 is outputted to the decoder 140. The decoder 140 decodes the contents of the shift register 120 on the basis of the decode enable signal 131 and outputs a signal for selecting the frequency dividing ratio of a frequency divider 160 to a fluctuation deciding circuit 150 on the basis of the decoded result. The circuit 150 outputs a signal for specifying the final frequency dividing ratio under the consideration of 'fluctuation' to the frequency divider 160. |
