发明名称 GRAPHIC ENLARGING AND REDUCING CIRCUIT
摘要 PURPOSE:To execute an enlargement and reduction processing at high speed by simultaneously instructing the plural positions of picture elements to be overlapped or removed at high speed. CONSTITUTION:The position of the scanning direction of the picture elements to be overlapped and removed which are predetermined according to the enlargement ratio or the reduction ratio of a picture is stored in a picture element position storing part 2. A reduction and enlargement processing part 1 raster scans a graphic according to the contents stored in the picture element position storing part 2 and partially overlaps or removes and outputs picture data corresponding to an instructed picture element in the picture data obtained by reading for a picture element.
申请公布号 JPS63163981(A) 申请公布日期 1988.07.07
申请号 JP19860315005 申请日期 1986.12.26
申请人 FUJITSU LTD 发明人 SEKINE KOICHI
分类号 G06T3/40 主分类号 G06T3/40
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