| 摘要 |
PURPOSE:To solve the problem of signal delay due to distributed resistance when a word line is formed with a polycrystalline silicon layer, by forming capacitor electrodes so that one area of each electrode becomes larger than the other area with a bit line as a center, and connecting the word line made of polycrystalline silicon to a metal wiring layer on the part of the capacitor electrodes. CONSTITUTION:A memory cell Mc is constituted by an MOS transistor MOS-Tr, and a capacitor Cs, which are formed on a semiconductor substrate 11. In this memory device, each capacitor electrode 12 constituting the capacitor Cs is formed so that one area becomes larger than the other area with a bit line as a center with respect to the memory cell Mc. A polycrystalline silicon layer 18, which constitutes a word line, and a metal wiring layer 24 are connected through a contact window 13, which is formed in insulating films 19a and 20 provided between the layers 18 and 24. Thus the substantial resistance with respect to the word line W can be made small, and delay in signal can be effectively avoided. |
