发明名称 DELAY DETECTING CIRCUIT
摘要 PURPOSE:To prevent an output from being dropped due to the shift of carrier frequency by delaying a received wave by means of plural circuits having different delay times and selecting and outputting the maximum output out of outputs obtained by detecting the phases of outputs from respective delay circuits. CONSTITUTION:A signal from an input terminal 1 is delayed by a delay line 2 and different phase changes are applied to the delayed signal by plural phase shifters 51-5m. The phase-shifting amounts of the phase shifters 51-5m are changed respectively by phase obtained by dividing 2 equally into (m) sections. The outputs of the plural phase shifters 1-5m are individually detected by phase detectors 31-3m to find out outputs 41-4m and the maximum value out of the outputs 41-4m is selected. Consequently, the detected outputs can be prevented from being dropped due to the shear of carrier frequency or the shear of a delay time difference in the delay lines. The circuit is especially suitable for a high frequency band.
申请公布号 JPS63164509(A) 申请公布日期 1988.07.07
申请号 JP19860308150 申请日期 1986.12.26
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 TAJIMA KOJIRO;MIKI EISUKE;UTSUNOMIYA SHIGEKI
分类号 H03D3/06;H04L27/227 主分类号 H03D3/06
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