| 摘要 |
PURPOSE:To improve the transfer speed of data blocks and the processing efficiency of a CPU by continuously transferring plural data blocks in accordance with parameters stored in a transfer format register. CONSTITUTION:When a DMA transfer instruction is accepted by a CPU, an address counter 3 and a timing control signal generating part 4 read out a parameter 21 of a data block 71 from a transfer format register 2 and set it to the address counter 3, and DMA transfer is started from the start address. When the address counter 3 counts the number of transfer words of the data block 71, the end of transfer of the data block 71 is detected, and a parameter 22 of a data block 72 is set to the address counter 3 through the timing control signal generating part 4, and transfer of the data block 72 is started. Similarly, plural blocks are continuously transferred in accordance with respective parameters of data blocks stored in the transfer format register 2.
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