发明名称 Image memory control circuit
摘要 In an image memory control circuit, image data is processed efficiently and fast, without software, by feeding control signals to the components. It has a first inverting device, to invert data which is to be newly written into the bit plan memory, a second inverting device, to invert data which has been read from the bit plan memory, a gate device, to control transmission of data which has been read from the bit plan memory to the second inverting device, a data combining device, to combine data by calculation of either the logical product (OR) or the logical sum (AND) of the data of the first and second inverting devices, and a third inverting device, to invert the data which is synthesised by the data generation device. In this way, simplified data processing is reliably achieved, and time for data processing is saved.
申请公布号 DE3743923(A1) 申请公布日期 1988.07.07
申请号 DE19873743923 申请日期 1987.12.23
申请人 MINOLTA CAMERA K.K. 发明人 KADONO,TAKASHI
分类号 G09G5/00;B41J2/485;G06F3/12;G06F12/00;G06K15/12;G06T1/60;G09G5/22;G09G5/39;G11C7/00;H04N5/907;(IPC1-7):G06F15/66;G06K15/00 主分类号 G09G5/00
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