| 摘要 |
PURPOSE:To reduce error detection/correction time by dividing the result of matrix operation, adding one of divided results, storing it together with the other and adding one addition result to the other when the next clock pulse is given so as to decrease the effect by the delay time. CONSTITUTION:An output of syndrome register 1 is given to a majority decision circuit 20 and the output of a check matrix circuit 30 in the majority decision circuit 20 is divided and added by an adder circuit 40 respectively and the result of addition is stored in a storage circuit 50 and read out by the next clock pulse. Thus, in case of error detection/correction, the readout from the storage circuit 50 and the addition of the adder circuit 60 and the comparison by a comparator circuit 70 have only to be applied in the next clock pulse period and the delay time in each clock pulse period is decreased. Thus, the clock pulse frequency is improved substantially to reduce the processing time.
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