发明名称 LATCH SIGNAL GENERATING CIRCUIT FOR DYNAMIC SENSE AMPLIFIER
摘要 PURPOSE:To improve the operation margin of a sense margin by connecting a constant current circuit in series with a starting transistor (TR) so as to make the operation of the constant current circuit independent of the power supply voltage thereby limiting a current from a latch signal line at the starting to a prescribed value. CONSTITUTION:Plural signal generating circuits each consisting of TRs Q5, Q7 whose 1st input/output terminals are connected to a latch signal line S and whose control terminals are connected to clock signal lines P1, P2 and of constant current circuits Q6, Q8 inserted between a 2nd input/output terminal of the TR and a power supply line, are provided and a different clock signal from each signal generating circuit is applied to the clock signal lines P1, P2. A depletion MOSFET Q6 is inserted between the source of an enhancement MOSFET Q5 and the ground power supply line and the potential of the gate is brought into the same as that of the source, then the latch signal generating circuit is operated stably at a constant current absorbing capability without power supply voltage dependency at the starting and then the current capability of the latch signal generating circuit is improved by using the MOSFETs Q7, Q8 so as to attain very stable high speed operation.
申请公布号 JPS63161587(A) 申请公布日期 1988.07.05
申请号 JP19860315728 申请日期 1986.12.24
申请人 NEC CORP 发明人 TAKESHIMA TOSHIO
分类号 G11C11/409;G11C11/34 主分类号 G11C11/409
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