| 摘要 |
This circuit phase aligns a phase-varying input data stream with a local clock. The incoming data stream is sampled at four quadrature points and these samples are applied to Ex-Or gates to yield four disagreement signals which indicates whether or not a transition from binary 0 to 1, or vise versa, has occurred between any pair of samples. The in-phase (0 DEG ) and anti-phase (180 DEG ) samples are serially loaded into different but similar shift registers, the taps of which provide the output with earlier or later versions of the input data stream at either 0 DEG or 180 DEG . A control circuit analyzes the disagreement signals and provides control signals which determine which of the shift register taps is connected to the aligner output. The circuit can correct for phase slippage between input data and local clock of up to plus or minus several time slots.
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