| 摘要 |
PURPOSE:To attain the operation at a high speed and with low power consumption as a whole by increasing number of automatic zero amplifier stages of voltage comparatros being components of a 1st parallel AD converter more than the number of automatic zero amplifier stages of voltage comparators being components of a 2nd parallel AD conversion section. CONSTITUTION:The number of stages of automatic zero amplifier stages 10 of voltage comparators 3a-3c in the 1st parallel AD conversion section 1 deciding the high-order bit is increased more than the number of stages of automatic zero amplifier stages of voltage comparators 4a-4c in the 2nd parallel AD conversion section 2 deciding the low-order bit. Thus, the 1st parallel AD conversion section 1 is quickened in its operation and the operation margin is increased. Since the input difference voltage of voltage comaparators 3a-3c in the 1st parallel AD conversion section 1 is large, the power consumption is less. Moreover, low power consumption is attained regardless of a minute input difference voltage. Thus, the AD converter with high speed and low power consumption as a whole is obtained.
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