发明名称 METHOD AND APPARATUS FOR TIME DIVISION MULTIPLEX FOR BSI
摘要 PURPOSE:To preserve the BSI processing of a basic BSI processing PCM signal in a BSI processing multiplex PCM signal by applying BSI processing to form a basic PCM signal at each prescribed block of each incoming channel PCM signal at a basic PCM speed and multiplexing in the unit of BSI block. CONSTITUTION:The input PCM signal (i) is subject to bit serial BSI PCM signal while the BSI processing (e.g., the 8th bit is inverted and added) is applied at each block (e.g., 8-bit) in basic BSI (Bit Sequence Independence) processing circuits 201-20N. The BSI processing PCM signal is generated in the basic BSI processing circuit 201 at each input PCM signal (each channel). The BSI processing PCM signal corresponding to each channel is multiplexed in a multiplexing circuit 24 in the unit of BSI processing block, that is, in the unit of 9-bits and the result is outputted to a transmission circuit 26 as the multiplex PCM signal. Thus, the BSI processing applied at the speed of the basic PCM signal takes over as it is even in the BSI processing multiplex PCM signal.
申请公布号 JPS63160438(A) 申请公布日期 1988.07.04
申请号 JP19860312635 申请日期 1986.12.24
申请人 FUJITSU LTD 发明人 IGUCHI KAZUO;SOEJIMA TETSUO;MURANO KAZUO;OHATA MICHINOBU;TAKEO HIROSHI
分类号 H04J3/00 主分类号 H04J3/00
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