| 摘要 |
PURPOSE:To obtain a sufficient phase fluctuation allowable value with a slight area by preventing the overlap of a signal setting a 1st bistable circuit to one stable state and a signal setting it to the other stable state. CONSTITUTION:A NOR gate 14 and a NOR gate 152 of a RS flip-flop 15 directly coupled in a conventional circuit are provided with an OR gate 30, a D flip-flop 31, an OR gate 32, a RS flip-flop 33, a D flip-flop 34, and a NOR gate 35 are provided to control the transfer of a set signal to the RS flip-flop 15. That is, a gate means inhibits the latching one stable state of the 1st bistable state circuit or the supply of the output of the 3rd latch means to the 1st bistable circuit during the 1st or 2nd clock generating state. Moreover, a 4th latch means latches the other stable state of the 1st bistable circuit and the output of a 3rd latch means is supplied to the 1st bistable circuit while the 1st and 2nd clocks are not generated. |
