| 摘要 |
PURPOSE:To reduce the chip area and to facilitate the serial access consecutively by using two series of sense amplifiers alternately so as to eliminate the need for the data transfer cycle. CONSTITUTION:One word line in response to the address signal is selected by the operation of a row address buffer 2 and a row decoder/driver 3 and storage information of n-set of memory cells is read in the bit line corresponding thereto. In this case, a gate 71 of the memory cell array 1 is opened, a minute potential of the bit line is amplified by the sense amplifier 81 and then the gate 71 is closed. Then a serial address counter 11 is operated, a selector 101 controls a multiplexer 91, one of the information of the n-set of sense amplifiers 81 is fed sequentially to an input/output buffer 12 and the data is read serially. Then the next row address is generated by an internal row address generating up-down counter 4 during this time and the serial data is read continuously by the similar cycle.
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